The advances realized in the Intel 4 process sustain Moore’s Law by doubling the achievable transistor density relative to Intel 7, the process node formerly known as 10nm Enhanced Super Fin (10ESF).
... [+]As the figure shows, individual features – including the contacted gate pitch, the fin pitch, and the interconnect pitch – have all shrunk. In addition, a previously announced innovation for this process node appears as pink cross-hatched rectangles in the figure above. Those rectangles represent “dummy gates,” which are required to electrically isolate adjacent FinFETs.
However, Sell explained that Intel 4 cuts the number of fins needed per transistor by using “enhanced copper” to reduce trace impedance in the chip’s lower metal signal layers. Together with the additional capacitance reduction that results from scaling, Intel was able to reduce the number of fins per transistor in the Intel 4 cell library without hurting performance.
However, the Intel 3 process node is, itself, an interim step. Intel 20A, the first of the company’s “Angstrom Era” nodes, will ditch the aging FinFETs in favor of the even more 3-dimensional RibbonFET transistors, which other semiconductor makers call GAA transistors. RibbonFETs will significantly boost transistor density yet again by stacking multiple transistor channels vertically on top of each other instead of laying channel fins down side by side as is done with FinFETs.
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